Field Programmable Gate Arrays (FPGAs) are a technology that sits between general-purpose microprocessors and fixed-structure Application Specific Integrated Circuits. This course covers specific topics related to FPGA development.
Field Programmable Gate Arrays (FPGAs) provide both the ability to effectively design your own processor to perform a specific task yet, at the same time, allows for later reprogramming the processor in the field. This course, FPGA Development in VHDL: Beyond the Basics, is a follow-up course to the Getting Started with FPGA Development using VHDL course. It covers several specific topics related to FPGA development. First, you'll learn about developing for the FPGA, and working with custom data types. Next, you'll explore working with attributes as well as subprograms and packages. Finally, you'll learn about the construction of stat machines and how to test your design. By the end this course, you'll improve your understanding of how to write programs for an FPGA and be proficient in testing your designs.
Course Overview Hi everyone. My name is Dmitri Nesteruk, and I'd like to welcome you to my course entitled More FPGA Development with VHDL. I am myself a Quantitative Analyst and particularly interested in the use of high performance computing technologies, such as FPGAs in the field of finance. Now this course builds on the material presented in the introductory VHDL course, and covers more topics related to VHDL programming, including new pieces of VHDL syntax, new toolset functionality, as well as useful development practices. So, in this course, we're going to cover the following modules. We'll get started by discussing developing for the FPGAs. We'll talk about working with custom data types, working with attributes, we'll discuss subprograms and packages, we'll take a look at the construction of state machines, and we'll finish off by discussing how to test your designs. By the end of the course, you'll improve your understanding of how to write programs for an FPGA, and how to test your designs as well. The key requirement for this course is you need to be familiar with FPGAs and the VHDL programming language, so to pick up those skills, check out the Introduction to FPGAs with VHDL course. I hope you will join me on this journey to learn about FPGAs with the More FPGA Programming with VHDL course here on Pluralsight.
Working with Custom Data Types Hi there, and welcome to this module on Working with Custom Data Types. Now we've already seen data types in the introductory course, so this module is an extension of that. The goal of this particular module is to gain a deeper understanding of the VHDL built-in types, as well as how to define your own custom data types. So here is what we're going to see in this module. First of all, well do a brief recap of the things that we've seen in the introductory course. Then we're going to talk about arrays and ranges. These two concepts are tightly coupled together, and we're going to discuss them together. Then we're going to talk about subtypes. We'll take a look at how to use subtypes to define multidimensional arrays. We'll talk about record types, we'll take a look at physical types, and then we're going to take a look at a simple demo where some of these data type concepts are going to be applied.
Monitoring Signal States with Attributes Hi there. In this module, we're going to talk about attributes, and one of the things we'll see is Monitoring Signal States with Attributes, but we're also going to see a lot of other attributes besides the signal related ones. So, the goal of this module is to gain in-depth knowledge about the predefined attributes which are built into VHDL, but we are also going to talk about defining our own attributes. So here's what we're going to see in this module. First of all, we'll discuss what attributes actually are, and what purpose they serve. Then we'll take a look at value kind attributes, function kind attributes, signal kind attributes, type kind attributes, range kind attributes, and finally, we'll take a look at user-defined attributes.
Keeping Code Organized with Subprograms and Packages Hi there. In this module, we're going to take a look at how to keep your code organized, and this is something that we've already looked at in the introductory course, but now we're going to take a look at a few more features that we've missed. So, the goal of this module is very simple. We're going to learn about some of the aspects of VHDL which help you write fewer lines of code and help you compact your code in different kinds of ways. So what are we going to see in this module? Well, first of all, we'll do a very brief recap of the things that you should have met already as part of the introductory course. Then we're going to talk about subprograms, and we're going to specifically discuss procedures. Now, there are two types of subprograms which are supported in VHDL. One is functions that we've met in the intro course, and the other is procedures, that's what we're going to cover here. Then we're going to talk about constants, a very simple idea, and then we're going to have two demos, so we're going to have a demo on generics, and we're going to have another demo on resolution functions.
Constructing State Machines Hello, and welcome to yet another module in our never-ending investigations of VHDL. Now, in this module we're going to talk about state machines. So, the goal of this module is to learn what state machines are, to learn about the different types of state machines, and how to represent them using VHDL. So let's take a look at what we're going to see in this module. First of all, we'll talk about what a state machine actually is. We'll take a look at the two different types of state machines that you can build, and then we'll take a look at two demos. So, the first demo, the simpler of the two, we're going to build traffic lights, essentially just a system which cycles different traffic lights around, and then we're going to look at a more complicated demo where we're going to build a combination lock. Finally, we're going to talk about state encoding styles, which are ways of giving hints to the synthesis engine on how to treat your state machine enumerations.
Testing Your Designs Hi there. In this module, we're going to talk about how to test your designs, meaning that we want to learn how to test the VHDL code that you've written before you actually flash the device and see it in action. So, the goal of this entire module is to learn how to make something called a testbench, and then we're also going to take a look at, say, framework, which automate unit tests, and that's going to be useful, for example, if you want to run unit tests on some sort of continuous integration server. So, here is what we're going to see in this module. First of all, we'll talk about testing generally and what testbenches are, then we're going to write a sample testbench for a very small circuit, and then we're going to take a look at VUnit, which is a framework which can help us with testing.